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22897ha (ot) no. 5483-1/25 overview the lc662304a, lc662306a, lc662308a, lc662312a, and lc662316a are 4-bit cmos microcontrollers that integrate on a single chip all the functions required in a special-purpose telephone controller, including rom, ram, i/o ports, a serial interface, a dtmf generator, timers, and interrupt functions. these microcontrollers are available in a 42-pin package. features and functions on-chip rom capacities of 4, 6, 8, 12, and 16 kilobytes, and an on-chip ram capacity of 512 4 bits. fully supports the lc66000 series common instruction set (128 instructions). i/o ports: 36 pins dtmf generator this microcontroller incorporates a circuit that can generate two sine wave outputs, dtmf output, or a melody output for software applications. 8-bit serial interface: one circuit instruction cycle time: 0.95 to 10 ? (at 3.0 to 5.5 v) powerful timer functions and prescalers time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer. time limit timer, event counter, pwm output, and square wave output using an 8-bit timer. time base function using a 12-bit prescaler. powerful interrupt system with 10 interrupt factors and 7 interrupt vector locations. external interrupts: 3 factors/3 vector locations internal interrupts: 4 factors/4 vector locations (waveform output internal interrupts: 3 factors and 1 vector; shared with external expansion interrupts) flexible i/o functions selectable options include 20-ma drive outputs, inverter circuits, pull-up and open drain circuits. optional runaway detection function (watchdog timer) 8-bit i/o functions power saving functions using halt and hold modes. packages: dip42s, qip48e (qfp48e) evaluation lsis: lc66599 (evaluation chip) + eva800/850-tb662yxx2 lc66e2316(on-chip eprom microcontroller) package dimensions unit: mm 3025b-dip42s preliminary lc662304a, 662306a, 662308a, 662312a, 662316a sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110 japan four-bit single-chip microcontrollers with 4, 6, 8, 12, and 16 kb of on-chip rom cmos lsi sanyo: dip42s 1 37.9 0.95 0.48 1.78 1.15 15.24 13.8 0.25 3.8 4.25 0.51 min 5.1 max 22 21 42 [lc662304a/662306a/662308a/662312a/662316a] unit: mm 3156-qfp48e (stand off) 1.5 17.2 17.2 1.5 1.5 1.5 1.6 1.6 14.0 0.35 15.6 0.8 1.0 1.0 3.0max 2.70 0.1 0.15 112 24 25 13 48 36 14.0 37 sanyo: qfp48e [lc662304a/662306a/662308a/662312a/662316a] no. 5483
series organization note: * under development no. 5483-2/25 lc662304a, 662306a, 662308a, 662312a, 662316a type no. no. of rom capacity ram package features pins capacity lc66304a/306a/308a 42 4 k/6 k/8 kb 512 w dip42s qfp48e lc66404a/406a/408a 42 4 k/6 k/8 kb 512 w dip42s qfp48e lc66506b/508b/512b/516b 64 6 k/8 k/12 k/16 kb 512 w dip64s qfp64a lc66354a/356a/358a 42 4 k/6 k/8 kb 512 w dip42s qfp48e lc66354s/356s/358s 42 4 k/6 k/8 kb 512 w qfp44m lc66556a/558a/562a/566a 64 6 k/8 k/12 k/16 kb 512 w dip64s qfp64e lc66354b/356b/358b 42 4 k/6 k/8 kb 512 w dip42s qfp48e low-voltage high-speed versions lc66556b/558b/562b/566b 64 6 k/8 k/12 k/16 kb 512 w dip64s qfp64e 3.0 to 5.5 v/0.92 ? lc66354c/356c/358c 42 4 k/6 k/8 kb 512 w dip42s qfp48e 2.5 to 5.5 v/0.92 ? lc662104a/06a/08a 30 4 k/6 k/8 kb 384 w dip30sd mfp30s lc662304a/06a/08a/12a/16a 42 4 k/6 k/8 k/12 k/16 kb 512 w dip42s qfp48e lc662508a/12a/16a 64 8 k/12 k/16 kb 512 w dip64s qfp64e lc665304a/06a/08a/12a/16a 48 4 k/6 k/8 k/12 k/16 kb 512 w dip48s qfp48e dual oscillator support 3.0 to 5.5 v/0.95 ? lc66e308 42 eprom 8 kb 512 w dic42s qfc48 with window with window lc66p308 42 otprom 8 kb 512 w dip42s qfp48e lc66e408 42 eprom 8 kb 512 w dic42s qfc48 with window with window lc66p408 42 otprom 8 kb 512 w dip42s qfp48e lc66e516 64 eprom 16 kb 512 w dic64s qfc64 with window with window lc66p516 64 otprom 16 kb 512 w dip64s qfp64e lc66e2108 * 30 eprom 8 kb 384 w lc66e2316 42 eprom 16 kb 512 w dic42s qfc48 with window with window lc66e2516 64 eprom 16 kb 512 w dic64s qfc64 with window with window lc66e5316 52/48 eprom 16 kb 512 w dic52s qfc48 with window with window lc66p2108 * 30 otprom 8 kb 384 w dip30sd mfp30s lc66p2316 * 42 otprom 16 kb 512 w dip42s qfp48e lc66p2516 64 otprom 16 kb 512 w dip64s qfp64e lc66p5316 48 otprom 16 kb 512 w dip48s qfp48e otp 4.0 to 5.5 v/0.95 ? window evaluation versions 4.5 to 5.5 v/0.92 ? window and otp evaluation versions 4.5 to 5.5 v/0.92 ? on-chip dtmf generator versions 3.0 to 5.5 v/0.95 ? low-voltage versions 2.2 to 5.5 v/3.92 ? normal versions 4.0 to 6.0 v/0.92 ?
pin assignments we recommend the use of reflow-soldering techniques to solder-mount qfp packages. please consult with your sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques). no. 5483-3/25 lc662304a, 662306a, 662308a, 662312a, 662316a 1 dip42s p20/si0 2 p21/so0 3 p22/sck0 4 p23/int0 5 p30/int1 6 p31/pout0 7 p32/pout1 8 v ss 9 osc1 10 osc2 11 v dd 12 res 13 pe0 14 pe1 15 test 16 p33/hold 17 p40/inv01 18 p41/inv00 19 p42/inv11 20 p43/inv10 21 p50 42 p13 41 p12 40 p11 39 p10 38 p03 37 p02 36 p01 35 p00 34 pd3/inv30 lc662304a 2306a 2308a 2312a 2316a 33 pd2/inv31 32 pd1/inv20 31 pd0/inv21 30 pc3 29 pc2 28 p63/pin1 27 p62/dt 26 p61 25 p60/ml 24 p53/int2 23 p52 22 p51 qfp48e lc662304a 2306a 2308a 2312a 2316a 36 37 p03 p02 1 p31/pout0 35 p01 2 p32/pout1 34 p00 3 v ss 33 pd3/inv3o 4 osc1 32 pd2/inv3i 5 osc2 31 pd1/inv2o 6 nc 30 nc 7 v dd 29 pd0/inv2i 8 res 28 pc3 9 pe0 27 pc2 10 pe1 26 p63/pin 11 test 25 p62/dt 12 p33/hold 24 p61 38 p10 23 p60/ml 39 p11 22 p53/int2 40 p12 21 p52 41 p13 20 p51 42 nc 19 nc 43 nc 18 nc 44 p20/si0 17 p50 45 p21/so0 16 p43/inv1o 46 p22/sck0 15 p42/inv1i 47 p23/int0 14 p41/inv0o 48 p30/int1 13 p40/inv0i top view
system block diagram differences between the lc663xx series and the lc6623xx series no. 5483-4/25 lc662304a, 662306a, 662308a, 662312a, 662316a item lc6630x series lc6635xb series lc6623xx series (including the lc66599 evaluation chip) system differences 65536 cycles 16384 cycles 16384 cycles hardware wait time (number of about 64 ms at 4 mhz (tcyc = 1 ?) about 16 ms at 4 mhz (tcyc = 1 ?) about 16 ms at 4 mhz (tcyc = 1 ?) cycles) when hold mode is cleared value of timer 0 after a reset (including the value after hold mode set to ff0. set to ffc. set to ffc. is cleared) dtmf generator none (tools are handled with none yes external devices.) inverter array none (tools are handled with none yes external devices.) sio1 yes yes none three-value inputs/comparator yes yes none inputs three-state output from p31 none none yes and p32 using p0 to clear halt mode in 4-bit groups in 4-bit groups can be specified for each bit. none for int3, int4, and int5. int3, int4, and int5 can be used external extended interrupts (tools are handled with external none for int3, int4, and int5. with the internal functions. devices.) shared with int2 other p53 functions (tools are handled with external shared with int2 shared with int2 devices.) differences in main characteristics lc66304a/306a/308a 3.0 to 5.5 v/0.92 to 10 ? operating power-supply voltage 4.0 to 6.0 v/0.92 t 10 ? lc6635xa 3.0 to 5.5 v/0.95 to 10 ? and operating speed (cycle time) lc66e308/p308 2.2 to 5.5 v/3.92 to 10 ? 4.5 to 5.5 v/0.92 to 10 ? 3.0 to 5.5 v/1.96 to 10 ? pull-up resistors p0, p1, p4, and p5: about 3 to 10 k p0, p1, p4, and p5: about 3 to 10 k p0, p1, p4, and p5: about 100 k p2 to p6 and pc: 15-v handling p2 to p6 and pc: 15-v handling p2, p3, p61, and p63: 12-v voltage port voltage handling p0, p1, pd, pe: normal voltage p0, p1, pd, pe: normal voltage handling others: normal voltage handling handling handling system control ram stack (512w) sp e a rom 4k/6k/8k/12k/16kb pc pout0 si0 so0 sck0 int1, int2 pin1, pout1 inv x o inv x i (x=0 to 3) flag dtmf gen. interrupt control mpx mpx timer1 mpx timer0 serial i/o 0 pe pd pc e m r d p y d p x d p l d p h p0 p1 p2 p3 p4 p5 p6 cz alu res ml dt test osc1 osc2 hold int0 prescaler
pin function overview no. 5483-5/25 lc662304a, 662306a, 662308a, 662312a, 662316a pin i/o overview output driver type options state after a standby mode reset operation p00 p01 p02 p03 p10 p11 p12 p13 p20/si0 p21/so0 p22/sck0 p23/int0 p30/int1 p31/pout0 p32/pout1 p33/hold p40/inv0i p41/inv0o p42/inv1i p43/inv1o i/o ports p00 to p03 input or output in 4-bit or 1-bit units p00 to p03 support the halt mode control function (this function can be specified in bit units.) i/o ports p10 to p13 input or output in 4-bit or 1-bit units i/o ports p20 to p23 input or output in 4-bit or 1-bit units p20 is also used as the serial input si0 pin. p21 is also used as the serial output so0 pin. p22 is also used as the serial clock sck0 pin. p23 is also used as the int0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input. i/o ports p30 to p32 input or output in 3-bit or 1-bit units p30 is also used as the int1 interrupt request. p31 is also used for the square wave output from timer 0. p32 is also used for the square wave and pwm output from timer 1. p31 and p32 also support 3-state outputs. hold mode control input hold mode is set up by the hold instruction when hold is low. in hold mode, the cpu is restarted by setting hold to the high level. this pin can be used as input port p33 along with p30 to p32. when the p33/hold pin is at the low level, the cpu will not be reset by a low level on the res pin. therefore, applications must not set p33/hold low when power is first applied. i/o ports p40 to p43 input or output in 4-bit or 1-bit units input or output in 8-bit units when used in conjunction with p50 to p53. can be used for output of 8-bit rom data when used in conjunction with p50 to p53. dedicated inverter circuit (option) i/o i/o i/o i/o i i/o pch: pull-up mos type nch: intermediate sink current type pch: pull-up mos type nch: intermediate sink current type pch: cmos type nch: intermediate sink current type nch: +12-v handling when od option selected pch: cmos type nch: intermediate sink current type nch: +12-v handling when od option selected pch: pull-up mos type cmos type when the inverter circuit option is selected nch: intermediate sink current type pull-up mos or nch od output output level on reset pull-up mos or nch od output output level on reset cmos or nch od output cmos or nch od output pull-up mos or nch od output output level on reset inverter circuit high or low (option) high or low (option) h h high or low or inverter i/o (option) hold mode: output off hold mode: output off hold mode: output off hold mode: output off hold mode: port output off, inverter output off halt mode: port output retained, inverter output continues halt mode: output retained halt mode: output retained halt mode: output retained halt mode: output retained continued on next page.
continued from preceding page. note: pull-up mos type: the output circuit includes a mos transistor that pulls the pin up to v dd . cmos output: complementary output. od output: open-drain output. no. 5483-6/25 lc662304a, 662306a, 662308a, 662312a, 662316a pin i/o overview output driver type options state after a standby mode reset operation p50 p51 p52 p53/int2 p60/ml p61 p62/dt p63/pin1 pc2 pc3 pd0/inv2i pd1/inv2o pd2/inv3i pd3/inv4o pe0 pe1 osc1 osc2 res test v dd v ss i/o ports p50 to p53 input or output in 4-bit or 1-bit units input or output in 8-bit units when used in conjunction with p40 to p43. can be used for output of 8-bit rom data when used in conjunction with p40 to p43. p53 is also used as the int2 interrupt request. i/o ports p60 to p63 input or output in 4-bit or 1-bit units p60 is also used as the melody output ml pin. p62 is also used as the tone output dt pin. p63 is also used for the event count input to timer 1. i/o ports pc2 to pc3 output in 2-bit or 1-bit units dedicated input ports pd0 to pd3 dedicated inverter circuits (option) dedicated input ports system clock oscillator connections when an external clock is used, leave osc2 open and connect the clock signal to osc1. system reset input when the p33/hold pin is at the high level, a low level input to the res pin will initialize the cpu. cpu test pin this pin must be connected to v ss during normal operation. power supply pins i/o i/o i/o i i i o i i pch: pull-up mos type nch: intermediate sink current type pch: cmos type nch: intermediate sink current type nch: +12-v handling when od option selected (p61 and p63 only) pch: cmos type nch: intermediate sink current type when the inverter circuit option is selected. pch: cmos type nch: intermediate sink current type pull-up mos or nch od output output level on reset cmos or nch od output cmos or nch od output inverter circuits ceramic oscillator or external clock selection high or low (option) h h normal input or inverter i/o (option) normal input option selection hold mode: output off hold mode: output off hold mode: port output off inverter hold mode: output off halt mode: output continues hold mode: oscillator stops halt mode: oscillator continues halt mode: port output retained halt mode: output retained halt mode: output retained
user options 1. port 0, 1, 4, and 5 output level at reset option the output levels at reset for i/o ports 0, 1, 4, and 5 in independent 4-bit groups, can be selected from the following two options. 2. oscillator circuit options main clock note: there is no rc oscillator option. 3. watchdog timer option a runaway detection function (watchdog timer) can be selected as an option. 4. port output type options the output type of each bit (pin) in ports p0, p1, p2, p3 (except for the p33/hold pin), p4, p5, p6, and pc can be selected individually from the following two options. no. 5483-7/25 lc662304a, 662306a, 662308a, 662312a, 662316a option circuit conditions and notes 1. external clock 2. ceramic oscillator the input has schmitt characteristics option conditions and notes 1. output high at reset the four bits of ports 0, 1, 4, or 5 are set in a group 2. output low at reset the four bits of ports 0, 1, 4, or 5 are set in a group option circuit conditions and notes 1. open-drain output 2. output with built-in pull-up resistor the port p2, p3, p5, and p6 inputs have schmitt characteristics. the port p2, p3, p5, and p6 inputs have schmitt characteristics. the cmos outputs (ports p2, p3, p6, and pc) and the pull-up mos outputs (p0, p1, p4, and p5) are distinguished by the drive capacity of the p-channel transistor. osc1 osc1 osc2 c1 c2 ceramic oscillator dsb output data input data dsb output data input data
5. inverter array circuit option one of the following options can be selected for each of the following port sets: p40/p41, p42/p43, pd0/pd1, and pd2/pd3. (pds do not use option 1 because they are dedicated to input.) no. 5483-8/25 lc662304a, 662306a, 662308a, 662312a, 662316a option circuit conditions and notes 1. normal port i/o circuit 2. inverter i/o circuit when the open-drain output type is selected when the built-in pull-up resistor output type is selected if this option is selected, the i/o circuit is disabled by the dsb signal. also note that the open-drain port output type option and the high level at reset option must be selected. dsb output data input data dsb output data input data dsb dsb input output output data high input data output data high input data
lc662316 series option data area and definitions lc662304a, 662306a, 662308a, 662312a, 662316a rom area bit option specified option/data relationship 7p5 output level at reset 0 = high level, 1 = low level 6p4 5 unused this bit must be set to 0. 3ff0h 4 oscillator option 0 = external clock, 1 = ceramic oscillator 3 unused this bit must be set to 0. 2p1 output level at reset 0 = low level, 1 = high level 1p0 0 watchdog timer option 0 = none, 1 = yes 7 p13 6 p12 output type 0 = od, 1 = pu 5 p11 3ff1h 4 p10 3 p03 2 p02 output type 0 = od, 1 = pu 1 p01 0 p00 7 unused this bit must be set to 0. 6 p32 5 p31 output type 0 = od, 1 = pu 3ff2h 4 p30 3 p23 2 p22 output type 0 = od, 1 = pu 1 p21 0 p20 7 p53 6 p52 output type 0 = od, 1 = pu 5 p51 3ff3h 4 p50 3 p43 2 p42 output type 0 = od, 1 = pu 1 p41 0 p40 7 6 unused this bit must be set to 0. 5 3ff4h 4 3 p63 2 p62 output type 0 = od, 1 = pu 1 p61 0 p60 7 6 unused this bit must be set to 0. 5 3ff5h 4 3 2 unused this bit must be set to 0. 1 0 7 6 unused this bit must be set to 0. 5 3ff6h 4 3 2 unused this bit must be set to 0. 1 0 continued on next page.
continued from preceding page. no. 5483-10/25 lc662304a, 662306a, 662308a, 662312a, 662316a rom area bit option specified option/data relationship 7 6 unused this bit must be set to 0. 5 3ff7h 4 3 pc3 output type 0 = od, 1 = pu 2 pc2 1 unused this bit must be set to 0. 0 7 ml disabled option 0 = disabled, 1 = enabled 6 unused this bit must be set to 1. 5 unused this bit must be set to 1. 3ff8h 4 pd3 inverter output 0 = inverter output, 1 = none 3 pd1 2 unused this bit must be set to 1. 1 p43 inverter output 0 = inverter output, 1 = none 0 p41 7 6 unused this bit must be set to 0. 5 3ff9h 4 3 2 unused this bit must be set to 0. 1 0 7 6 unused this bit must be set to 0. 5 3ffah 4 3 2 unused this bit must be set to 0. 1 0 7 6 unused this bit must be set to 0. 5 3ffbh 4 3 2 unused this bit must be set to 0. 1 0 7 6 unused this bit must be set to 0. 5 3ffch 4 3 2 unused this bit must be set to 0. 1 0 7 6 5 3ffdh 4 reserved. must be set to predefined data values. this data is generated by the assembler. 3 if the assembler is not used, set this data to ?0? 2 1 0 continued on next page.
continued from preceding page. specifications absolute maximum ratings at ta = 25?, v ss = 0 v note: 1. applies to pins with open-drain output specifications. for pins with other than open-drain output specifications, the ratings in the pin column for that pin apply. 2. for the oscillator input and output pins, levels up to the free-running oscillation level are allowed. 3. sink current (applies to pd when the inverter array specifications are selected.) 4. source current (applies to all pins except pd for which the pull-up output specifications, the cmos output specifications, or the inverter array specifications have been selected. applies to pd pins for which the inverter array specifications have been selected.) 5. we recommend the use of reflow soldering techniques to solder mount qfp packages. please consult with your sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques). no. 5483-11/25 lc662304a, 662306a, 662308a, 662312a, 662316a rom area bit option specified option/data relationship 7 6 5 3ffeh 4 reserved. must be set to predefined data values. this data is generated by the assembler. 3 if the assembler is not used, set this data to ?0? 2 1 0 7 6 5 3fffh 4 reserved. must be set to predefined data values. this data is generated by the assembler. 3 if the assembler is not used, set this data to ?0? 2 1 0 parameter symbol conditions ratings unit note maximum supply voltage v dd max v dd ?.3 to +7.0 v v in 1 p2, p3 (except for the p33/hold pin), ?.3 to +12.0 v 1 input voltage p61, and p63 v in 2 all other inputs ?.3 to v dd + 0.3 v 2 v out 1 p2, p3 (except for the p33/hold pin), ?.3 to +12.0 v 1 output voltage p61, and p63 v out 2 all other inputs ?.3 to v dd + 0.3 v 2 i on 1 p0, p1, p2, p3 (except for the p33/hold pin), 20 ma 3 p4, p5, p6, pc output current per pin i on 2 p41, p43, pc3, pd1, pd3 20 ma 3 ? op 1 p0, p1, p4, p5 2 ma 4 ? op 2 p2, p3 (except for the p33/hold pin), p6, and pc 4 ma 4 ? op 3 p41, p43, pc3, pd1, pd3 10 ma 4 s i on 1 p0, p1, p2, p3 (except for the p33/hold pin), pd 75 ma 3 total pin current s i on 2 p4, p5, p6, pc 75 ma 3 s i op 1 p0, p1, p2, p3 (except for the p33/hold pin), pd 25 ma 4 s i op 2 p4, p5, p6, pc 25 ma 4 allowable power dissipation pd max ta = ?0 to +70?: dip42s (qfp48e) 600 (430) mw 5 operating temperature topr ?0 to +70 ? storage temperature tstg ?5 to +125 ?
allowable operating ranges at ta = ?0 to +70?, v ss = 0 v, v dd = 3.0 to 5.5 v, unless otherwise specified. note: 1. applies to pins with open-drain specifications. however, v ih 2 applies to the p33/hold pin. when ports p2, p3, and p6 have cmos output specifications they cannot be used as input pins. 2. pc port pins with cmos output specifications cannot be used as input pins. contact sanyo for details on the allowable operating ranges for p4 and pd pins with inverter array specifications. no. 5483-12/25 lc662304a, 662306a, 662308a, 662312a, 662316a parameter symbol conditions min typ max unit note operating supply voltage v dd v dd 3.0 5.5 v memory retention supply voltage v dd hv dd : during hold mode 1.8 5.5 v v ih 1 p2, p3 (except for the p33/hold pin), 0.8 v dd 10.0 v 1 p61, and p63: n-channel output transistor off input high-level voltage v ih 2 p33/hold, res, osc1: 0.8 v dd v dd v n-channel output transistor off v ih 3 p0, p1, p4, p5, pc, pd, pe: 0.8 v dd v dd v2 n-channel output transistor off v il 1 p2, p3 (except for the p33/hold pin), p6, v ss 0.2 v dd v2 res, and osc1: n-channel output transistor off input low-level voltage v il 2 p33/hold: v dd = 1.8 to 5.5 v v ss 0.2 v dd v v il 3 p0, p1, p4, p5, pc, pd, pe, test: v ss 0.2 v dd v2 n-channel output transistor off operating frequency fop 0.4 4.20 mhz (instruction cycle time) (tcyc) (10) (0.95) (?) [external clock input conditions] osc1: defined by figure 1. input the clock frequency f ext signal to osc1 and leave osc2 open. 0.4 4.20 mhz (external clock input must be selected as the oscillator circuit option.) osc1: defined by figure 1. input the clock pulse width t exth , t extl signal to osc1 and leave osc2 open. 100 ns (external clock input must be selected as the oscillator circuit option.) osc1: defined by figure 1. input the clock rise and fall times t extr , t extf signal to osc1 and leave osc2 open. 30 ns (external clock input must be selected as the oscillator circuit option.)
electrical characteristics at ta = ?0 to +70?, v ss = 0 v, v dd = 3.0 to 5.5 v unless otherwise specified. no. 5483-13/25 lc662304a, 662306a, 662308a, 662312a, 662316a parameter symbol conditions min typ max unit note p2, p3 (except for the p33/hold pin), i ih 1 p61, and p63: v in = 10.0 v, with the output 5.0 ? 1 nch transistor off p0, p1, p4, p5, p6, pc, osc1, res, and input high-level current i ih 2 p33/hold (does not apply to pd, pe, pc2, 1.0 ? 1 pc3, p61, and p63.): v in = v dd , with the output nch transistor off i ih 3 pd, pe, pc2, pc3: v in = v dd , 1.0 ? 1 with the output nch transistor off i il 1 input ports other than pd, pe, pc2, and pc3: ?.0 ? 2 input low-level current v in = v ss , with the output nch transistor off i il 2 pc2, pc3, pd, pe: v in = v ss , ?.0 ? 2 with the output nch transistor off p2, p3 (except for the p33/hold pin), v dd ?1.0 output high-level voltage v oh 1 p6, and pc: i oh = ? ma v3 p2, p3 (except for the p33/hold pin), v dd ?0.5 p6, and pc: i oh = ?.1 ma value of the output pull-up resistor r po p0, p1, p4, p5 30 100 150 k 4 v ol 1 p0, p1, p2, p3, p4, p5, p6, and pc 0.4 v output low-level voltage (except for the p33/hold pin): i ol = 1.6 ma v ol 2 p0, p1, p2, p3, p4, p5, p6, and pc 1.5 v (except for the p33/hold pin): i ol = 8 ma i off 1 p2, p3, p61, p63: v in = v dd 5.0 ? 5 output off leakage current i off 2 does not apply to p2, p3, p61, and p63: 1.0 ? 5 v in = v dd [schmitt characteristics] hysteresis voltage v hys 0.1 v dd v high-level threshold voltage vt h p2, p3, p5, p6, osc1 (ext), res 0.5 v dd 0.8 v dd v low-level threshold voltage vt l 0.2 v dd 0.5 v dd v [ceramic oscillator] oscillator frequency f cf osc1, osc2: figure 2, 4 mhz 4.0 mhz oscillator stabilization time f cfs figure 3, 4 mhz 10.0 ms [serial clock] cycle time input t ckcy 0.9 ? output 2.0 tcyc low-level and high-level input t ckl 0.4 ? pulse widths output t ckh 1.0 tcyc rise an fall times output t ckr , t ckf 0.1 ? [serial input] data setup time t ick 0.3 ? data hold time t cki 0.3 ? [serial output] so0: with the timing of figure 4 and the test output delay time t cko load of figure 5. stipulated with respect to the 0.3 ? falling edge ( ) of sck0. si0: with the timing of figure 4. stipulated with respect to the rising edge ( - ) of sck0. sck0: with the timing of figure 4 and the test load of figure 5. continued on next page.
continued from preceding page. note: 1. with the output nch transistor off in shared i/o ports with the open-drain output specifications. these pins cannot be used as input pins if the cmos output specifications are selected. 2. with the output nch transistor off in shared i/o ports with the open-drain output specifications. the rating for the pull-up output specification pins is stipulated in terms of the output pull-up current ipo. these pins cannot be used as input pins if the cmos output specifications are selected. 3. with the output nch transistor off for cmos output specification pins. 4. with the output nch transistor off for pull-up output specification pins. 5. with the output nch transistor off for open-drain output specification pins. 6. reset state tone (dtmf) output characteristics dc characteristics at ta = ?0 to +70?, v ss = 0 v 1. when the mlout enable option is selected (the ml output function can be used) note * see item 2. below if the mlout disable mask option was selected. 2. when the mlout disable option is selected (the ml output function cannot be used) note * see item 1. above if the mlout enable mask option was selected. no. 5483-14/25 lc662304a, 662306a, 662308a, 662312a, 662316a parameter symbol conditions min typ max unit note [pulse conditions] int0: figure 6, conditions under which the int0 int0 high and low-level t ioh , t iol interrupt can be accepted, conditions under 2 tcyc which the timer 0 event counter or pulse width measurement input can be accepted high and low-level pulse widths t iih , t iil int1, int2: figure 6, conditions under which 2 tcyc for interrupt inputs other than int0 the corresponding interrupt can be accepted pin1 high and low-level t pinh , t pinl pin1: figure 6, conditions under which the 2 tcyc pulse widths timer 1 event counter input can be accepted res high and low-level t rsh , t rsl res: figure 6, conditions under which reset 3 tcyc pulse widths can be applied. operating current drain i dd op v dd : 4-mhz ceramic oscillator 4.5 8.0 ma 6 v dd : 4-mhz external clock 4.5 8.0 ma halt mode current drain i ddhalt v dd : 4-mhz ceramic oscillator 2.5 5.5 ma v dd : 4-mhz external clock 2.5 5.5 ma hold mode current drain i ddhold v dd : v dd = 1.8 to 5.5 v 0.01 10 ? parameter symbol conditions min typ max unit tone output voltage (p-p) v t1 dt: dual tones, v dd = 3.5 to 5.5 v * 0.9 1.3 2.0 v row/column tone output d bcr1 dt: dual tones, v dd = 3.5 to 5.5 v * 1.0 2.0 3.0 db voltage ratio tone distortion thd1 dt: single tone, v dd = 3.5 to 5.5 v * 27% parameter symbol conditions min typ max unit tone output voltage (p-p) v t1 dt: dual tones, v dd = 3.0 to 5.5 v * 0.9 1.3 2.0 v row/column tone output d bcr1 dt: dual tones, v dd = 3.0 to 5.5 v * 1.0 2.0 3.0 db voltage ratio tone distortion thd1 dt: single tone, v dd = 3.0 to 5.5 v * 27%
figure 1 external clock input waveform figure 2 ceramic oscillator circuit figure 3 oscillator stabilization period table 1 guaranteed ceramic oscillator constants external capacitor type figure 4 serial i/o timing figure 5 timing load no. 5483-15/25 lc662304a, 662306a, 662308a, 662312a, 662316a external capacitor type built-in capacitor type 4 mhz c1 = 33 pf 10% 4 mhz (murata mfg. co., ltd.) c2 = 33 pf 10% (murata mfg. co., ltd.) csa4.00mg cst4.00mg 4 mhz c1 = 33 pf 10% 4 mhz (kyocera corporation) c2 = 33 pf 10% (kyocera corporation) kbr4.0ms kbr4.0mes t extl open (osc2) osc1 t extr t extf v ss v dd 0.2v dd 0.8v dd 1/f ext t exth external clock osc2 osc1 c1 c2 ceramic oscillator v dd osc ov oscillator unstable period t cfs t ick t cki t ckl t ckr t ckcy t ckh t ckf 0.8v dd (input) v dd -1 (output) 0.2v dd sck0 sck1 si0 si1 so0 so1 0.4v dd 0.8v dd 0.2v dd t ck0 v dd -1 0.4v dd c=50pf test point r=1k
figure 6 input timing for the int0, int1, int2, pin1, and res pins figure 7 tone output pin load no. 5483-16/25 lc662304a, 662306a, 662308a, 662312a, 662316a t i0h t i1h t pinh t rsh t i0l t i1l t pinl t rsl 0.8v dd 0.2v dd p60/ml p62/dt r=10k
lc66xxxx series instruction table (by function) abbreviations: ac: accumulator e: e register cf: carry flag zf: zero flag hl: data pointer dph, dpl xy: data pointer dpx, dpy m: data memory m (hl): data memory pointed to by the dph, dpl data pointer m (xy): data memory pointed to by the dpx, dpy auxiliary data pointer m2 (hl): two words of data memory (starting on an even address) pointed to by the dph, dpl data pointer sp: stack pointer m2 (sp): two words of data memory pointed to by the stack pointer m4 (sp): four words of data memory pointed to by the stack pointer in: n bits of immediate data t2: bit specification pch: bits 8 to 11 in the pc pcm: bits 4 to 7 in the pc pcl: bits 0 to 3 in the pc fn: user flag, n = 0 to 15 timer0: timer 0 timer1: timer 1 sio: serial register p: port p (i4): port indicated by 4 bits of immediate data int: interrupt enable flag ( ), [ ]: indicates the contents of a location ? : transfer direction, result : exclusive or : logical and : logical or +: addition ? subtraction ? taking the one's complement no. 5483-17/25 lc662304a, 662306a, 662308a, 662312a, 662316a t2 11 10 01 00 bit 2 3 2 2 2 1 2 0
no. 5483-18/25 lc662304a, 662306a, 662308a, 662312a, 662316a continued on next page. instruction code affected mnemonic operation description status note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bits [accumulator manipulation instructions] cla clear ac 1000 0000 1 1 ac ? 0 clear ac. zf has a vertical (equivalent to lai 0.) skip function. daa decimal adjust ac 1100 1111 22 ac ? (ac) + 6 add six to ac. zf in addition 0010 0110 (equivalent to adi 6.) decimal adjust ac 1100 1111 ac ? (ac) + 10 das in subtraction 0010 1010 2 2 (equivalent to add 10 to ac. zf adi 0ah.) clc clear cf 0001 1110 1 1 cf ? 0 clear cf to 0. cf stc set cf 0001 1111 1 1 cf ? 1 set cf to 1. cf cma complement ac 0001 1000 1 1 ac ? (ac) take the one? complement zf of ac. ia increment ac 0001 0100 1 1 ac ? (ac) + 1 increment ac. zf, cf da decrement ac 0010 0100 1 1 ac ? (ac) ?1 decrement ac. zf, cf rotate ac right ac 3 ? (cf), rar through cf 0001 0000 1 1 acn ? (acn + 1), shift ac (including cf) right. cf cf ? (ac 0 ) rotate ac left ac 0 ? (cf), ral through cf 0000 0001 1 1 acn + 1 ? (acn), shift ac (including cf) left. cf, zf cf ? (ac 3 ) tae transfer ac to e 0100 0101 1 1 e ? (ac) move the contents of ac to e. tea transfer e to ac 0100 0110 1 1 ac ? (e) move the contents of e to ac. zf xae exchange ac with e 0100 0100 1 1 (ac) ? (e) exchange the contents of ac and e. [memory manipulation instructions] im increment m 0001 0010 1 1 m (hl) ? increment m (hl). zf, cf [m (hl)] + 1 dm decrement m 0010 0010 1 1 m (hl) ? decrement m (hl). zf, cf [m (hl)] ?1 imdr i8 increment m direct 1100 0111 2 2 m (i8) ? [m (i8)] + 1 increment m (i8). zf, cf i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 dmdr i8 decrement m direct 1100 0011 2 2 m (i8) ? [m (i8)] ?1 decrement m (i8). zf, cf i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 smb t2 set m data bit 0000 11t 1 t 0 1 1 [m (hl), t2] ? 1 set the bit in m (hl) specified by t0 and t1 to 1. rmb t2 reset m data bit 0010 11t 1 t 0 1 1 [m (hl), t2] ? 0 clear the bit in m (hl) zf specified by t0 and t1 to 0. [arithmetic, logic and comparison instructions] add the contents of ac and ad add m to ac 0000 0110 1 1 ac ? (ac) + m (hl) as two? complement zf, cf [m (hl)] values and store the result in ac. add the contents of ac and addr i8 add m direct to ac 1100 1001 2 2 ac ? (ac) + [m (i8)] m (i8) as two? complement zf, cf i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 values and store the result in ac. add the contents of ac, adc add m to ac with cf 0000 0010 1 1 ac ? (ac) + m (hl) and c as two? zf, cf [m (hl)] + (cf) complement values and store the result in ac. add the contents of ac and adi i4 add immediate data 1100 1111 22 ac ? (ac) + the immediate data as two? zf to ac 0010 i 3 i 2 i 1 i 0 i 3 , i 2 , i 1 , i 0 complement values and store the result in ac. subtract the contents of ac cf will be zero if subc subtract ac from m 0001 0111 1 1 ac ? [m (hl)] and cf from m (hl) as two? zf, cf there was a with cf (ac) ?(cf) complement values and store borrow and one the result in ac. otherwise. and m with ac then ac ? (ac) take the logical and of ac anda store ac 0000 0111 1 1 [m (hl)] and m (hl) and store the zf result in ac. or m with ac then ac ? (ac) take the logical or of ac and ora store ac 0000 0101 1 1 [m (hl)] m (hl) and store the result zf in ac. number of bytes number of cycles
continued from preceding page. no. 5483-19/25 lc662304a, 662306a, 662308a, 662312a, 662316a continued on next page. instruction code affected mnemonic operation description status note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bits [arithmetic, logic and comparison instructions] exclusive or m with ac ? (ac) take the logical exclusive or exl ac then store ac 0001 0101 1 1 [m (hl)] of ac and m (hl) and store zf the result in ac. and m with ac then m (hl) ? (ac) take the logical and of ac andm store m 0000 0011 1 1 [m (hl)] and m (hl) and store the zf result in m (hl). or m with ac then m (hl) ? (ac) take the logical or of ac and orm store m 0000 0100 1 1 [m (hl)] m (hl) and store the result zf in m (hl). compare the contents of ac and m (hl) and set or clear cf and zf according to the result. cm compare ac with m 0001 0110 1 1 [m (hl)] + (ac) + 1 zf, cf compare the contents of ac and the immediate data i 3 i 2 i 1 i 0 and set or clear cf and zf according to the result. ci i4 compare ac with 1100 1111 22i 3 i 2 i 1 i 0 + (ac) + 1 zf, cf immediate data 1010 i 3 i 2 i 1 i 0 zf ? 1 compare the contents of dp l cli i4 compare dp l with 1100 1111 22 if (dp l ) = i 3 i 2 i 1 i 0 with the immediate data. zf immediate data 1011 i 3 i 2 i 1 i 0 zf ? 0 set zf if identical and clear if (dp l ) i 3 i 2 i 1 i 0 zf if not. zf ? 1 if (ac, t2) = [m (hl), compare the corresponding cmb t2 compare ac bit with 1100 1111 22 t2] bits specified by t0 and t1 in zf m data bit 1101 00t 1 t 0 zf ? 0 ac and m (hl). set zf if if (ac, t2) [m (hl), identical and clear zf if not. t2] [load and store instructions] lae load ac and e from 0101 1100 1 1 ac ? m (hl), load the contents of m2 (hl) m2 (hl) e ? m (hl + 1) into ac, e. lai i4 load ac with 1000 i 3 i 2 i 1 i 0 1 1 ac ? i 3 i 2 i 1 i 0 load the immediate data zf has a vertical immediate data into ac. skip function ladr i8 load ac from m 1100 0001 2 2 ac ? [m (i8)] load the contents of m (i8) zf direct i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 into ac. s store ac to m 0100 0111 1 1 m (hl) ? (ac) store the contents of ac into m (hl). sae store ac and e to 0101 1110 1 1 m (hl) ? (ac) store the contents of ac, e m2 (hl) m (hl + 1) ? (e) into m2 (hl). load the contents of m (reg) into ac. the reg is either hl or xy load ac from depending on t 0 . la reg m (reg) 0100 10t 0 0 1 1 ac ? [m (reg)] zf number of bytes number of cycles magnitude cf zf comparison [m (hl)] > (ac) 0 0 [m (hl)] = (ac) 1 1 [m (hl)] < (ac) 1 0 magnitude cf zf comparison i 3 i 2 i 1 i 0 > ac 0 0 i 3 i 2 i 1 i 0 = ac 1 1 i 3 i 2 i 1 i 0 < ac 1 0 reg t 0 hl 0 xy 1
continued from preceding page. no. 5483-20/25 lc662304a, 662306a, 662308a, 662312a, 662316a continued on next page. instruction code affected mnemonic operation description status note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bits [load and store instructions] load the contents of m (reg) into ac. (the reg is either hl zf is set load ac from m (reg) ac ? [m (reg)] or xy.) then increment the according to the la reg, i then increment reg 0100 10t 0 11 2dp l ? (dp l ) + 1 contents of either dp l or dp y . zf result of or dp y ? (dp y ) + 1 the relationship between t 0 incrementing and reg is the same as that dp l or dp y . for the la reg instruction. load the contents of m (reg) into ac. (the reg is either hl zf is set load ac from m (reg) ac ? [m (reg)] or xy.) then decrement the according to the la reg, d then decrement reg 0101 10t 0 11 2dp l ? (dp l ) ?1 contents of either dp l or dp y . zf result of or dp y ? (dp y ) ?1 the relationship between t 0 decrementing and reg is the same as that dp l or dp y . for the la reg instruction. exchange the contents of m (reg) and ac. the reg is either hl or xy exchange ac with depending on t 0 . xa reg m (reg) 0100 11t 0 0 1 1 (ac) ? [m (reg)] exchange the contents of m (reg) and ac. (the reg is zf is set exchange ac with (ac) ? [m (reg)] either hl or xy.) then according to the xa reg, i m (reg) then 0100 11t 0 11 2dp l ? (dp l ) + 1 increment the contents of zf result of increment reg or dp y ? (dp y ) + 1 either dp l or dp y . the incrementing relationship between t 0 and dp l or dp y . reg is the same as that for the xa reg instruction. exchange the contents of m (reg) and ac. (the reg is zf is set exchange ac with (ac) ? [m (reg)] either hl or xy.) then according to the xa reg, d m (reg) then 0101 11t 0 11 2dp l ? (dp l ) ?1 decrement the contents of zf result of decrement reg or dp y ? (dp y ) ?1 either dp l or dp y . the decrementing relationship between t 0 and dp l or dp y . reg is the same as that for the xa reg instruction. xadr i8 exchange ac with 1100 1000 2 2 (ac) ? [m (i8)] exchange the contents of ac m direct i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 and m (i8). leai i8 load e & ac with 1100 0110 22 e ? i 7 i 6 i 5 i 4 load the immediate data i8 immediate data i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 ac ? i 3 i 2 i 1 i 0 into e, ac. load into e, ac the rom data rtbl read table data from 0101 1010 1 2 e, ac ? at the location determined by program rom [rom (pch, e, ac)] replacing the lower 8 bits of the pc with e, ac. output from ports 4 and 5 the read table data from port 4, 5 ? rom data at the location rtblp program rom then 0101 1000 1 2 [rom (pch, e, ac)] determined by replacing the output to p4, 5 lower 8 bits of the pc with e, ac. [data pointer manipulation instructions] load dp h with zero ldz i4 and dp l with 0110 i 3 i 2 i 1 i 0 11 dp h ? 0 load zero into dp h and the immediate data dpl ? i 3 i 2 i 1 i 0 immediate data i4 into dp l . respectively lhi i4 load dp h with 1100 1111 22dp h ? i 3 i 2 i 1 i 0 load the immediate data i4 immediate data 0000 i 3 i 2 i 1 i 0 into dp h . lli i4 load dp l with 1100 1111 22dp l ? i 3 i 2 i 1 i 0 load the immediate data i4 immediate data 0001 i 3 i 2 i 1 i 0 into dp l . lhli i8 load dp h , dp l with 1100 0000 22 dp h ? i 7 i 6 i 5 i 4 load the immediate data into immediate data i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 dp l ? i 3 i 2 i 1 i 0 dl h , dp l . lxyi i8 load dp x , dp y with 1100 0000 22 dp x ? i 7 i 6 i 5 i 4 load the immediate data into immediate data i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 dp y ? i 3 i 2 i 1 i 0 dl x , dp y . number of bytes number of cycles reg t 0 hl 0 xy 1
continued from preceding page. no. 5483-21/25 lc662304a, 662306a, 662308a, 662312a, 662316a continued on next page. instruction code affected mnemonic operation description status note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bits [data pointer manipulation instructions] il increment dp l 0001 0001 1 1 dp l ? (dp l ) + 1 increment the contents zf of dp l . dl decrement dp l 0010 0001 1 1 dp l ? (dp l ) ?1 decrement the contents zf of dp l . iy increment dp y 0001 0011 1 1 dp y ? (dp y ) + 1 increment the contents zf of dp y . dy decrement dp y 0010 0011 1 1 dp y ? (dp y ) ?1 decrement the contents zf of dp y . tah transfer ac to dp h 1100 1111 22dp h ? (ac) transfer the contents of ac 1111 0000 to dp h . tha transfer dp h to ac 1100 1111 2 2 ac ? (dp h ) transfer the contents of dp h zf 1110 0000 to ac. xah exchange ac 0100 0000 1 1 (ac) ? (dp h ) exchange the contents of ac with dp h and dp h . tal transfer ac to dp l 1100 1111 22dp l ? (ac) transfer the contents of ac 1111 0001 to dp l . tla transfer dp l to ac 1100 1111 2 2 ac ? (dp l ) transfer the contents of dp l zf 1110 0001 to ac. xal exchange ac 0100 0001 1 1 (ac) ? (dp l ) exchange the contents of ac with dp l and dp l . tax transfer ac to dp x 1100 1111 22dp x ? (ac) transfer the contents of ac 1111 0010 to dp x . txa transfer dp x to ac 1100 1111 2 2 ac ? (dp x ) transfer the contents of dp x zf 1110 0010 to ac. xax exchange ac 0100 0010 1 1 (ac) ? (dp x ) exchange the contents of ac with dp x and dp x . tay transfer ac to dp y 1100 1111 22dp y ? (ac) transfer the contents of ac 1111 0011 to dp y . tya transfer dp y to ac 1100 1111 2 2 ac ? (dp y ) transfer the contents of dp y zf 1110 0011 to ac. xay exchange ac 0100 0011 1 1 (ac) ? (dp y ) exchange the contents of ac with dp y and dp y . [flag manipulation instructions] sfb n4 set flag bit 0111 n 3 n 2 n 1 n 0 1 1 fn ? 1 set the flag specified by n4 to 1. rfb n4 reset flag bit 0011 n 3 n 2 n 1 n 0 1 1 fn ? 0 reset the flag specified zf by n4 to 0. [jump and subroutine instructions] pc13, 12 ? this becomes jmp jump in the current 1110p 11 p 10 p 9 p 8 pc13, 12 jump to the location in the pc12 + (pc12) addr bank p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 22 pc11 to 0 ? same bank specified by the immediately p 11 to p 8 immediate data p12. following a bank instruction. jump to the address pc13 to 8 ? jump to the location jpea stored at e and ac 0010 0111 1 1 pc13 to 8, determined by replacing the in the current page pc7 to 4 ? (e), lower 8 bits of the pc pc3 to 0 ? (ac) by e, ac. pc13 to 11 ? 0, pc10 to 0 ? cal call subroutine 0101 0p 10 p 9 p 8 22 p 10 to p 0 , call a subroutine. addr p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 m4 (sp) ? (cf, zf, pc13 to 0), sp ? (sp)-4 pc13 to 6, pc10 ? 0, czp call subroutine in the 1010 p 3 p 2 p 1 p 0 12 pc5 to 2 ? p 3 to p 0 , call a subroutine on page 0 addr zero page m4 (sp) ? in bank 0. (cf, zf, pc12 to 0), sp ? sp-4 bank change bank 0001 1011 1 1 change the memory bank and register bank. number of bytes number of cycles
continued from preceding page. no. 5483-22/25 lc662304a, 662306a, 662308a, 662312a, 662316a instruction code affected mnemonic operation description status note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bits [jump and subroutine instructions] store the contents of reg in m2 (sp). subtract 2 from sp after the store. push push reg on m2 (sp) 1100 1111 22 m2 (sp) ? (reg) reg 1111 1i 1 i 0 0 sp ? (sp) ?2 add 2 to sp and then load the pop 1100 1111 sp ? (sp) + 2 contents of m2(sp) into reg. reg pop reg off m2 (sp) 1110 1i 1 i 0 0 22 reg ? [m2 (sp)] the relation between i1i0 and reg is the same as that for the push reg instruction. return from sp ? (sp) + 4 return from a subroutine or rt subroutine 0001 1100 1 2 pc ? [m4 (sp)] interrupt handling routine. zf and cf are not restored. return from interrupt sp ? (sp) + 4 return from a subroutine or rti routine 0001 1101 1 2 pc ? [m4 (sp)] interrupt handling routine. zf zf, cf cf, zf ? [m4 (sp)] and cf are restored. [branch instructions] pc7 to 0 ? branch to the location in the bat2 branch on ac bit 1101 00t 1 t 0 22 p 7 p 6 p 5 p 4 same page specified by p 7 to addr p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 p 3 p 2 p 1 p 0 p 0 if the bit in ac specified by if (ac, t2) = 1 the immediate data t 1 t 0 is one. pc7 to 0 ? branch to the location in the bnat2 branch on no ac bit 1001 00t 1 t 0 22 p 7 p 6 p 5 p 4 same page specified by p 7 to addr p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 p 3 p 2 p 1 p 0 p 0 if the bit in ac specified by if (ac, t2) = 0 the immediate data t 1 t 0 is zero. pc7 to 0 ? branch to the location in the bmt2 1101 01t 1 t 0 p 7 p 6 p 5 p 4 same page specified by p 7 to addr branch on m bit p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 22 p 3 p 2 p 1 p 0 p 0 if the bit in m (hl) specified if [m (hl),t2] by the immediate data t 1 t 0 = 1 is one. pc7 to 0 ? branch to the location in the bnmt2 1001 01t 1 t 0 p 7 p 6 p 5 p 4 same page specified by p 7 to addr branch on no m bit p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 22 p 3 p 2 p 1 p 0 p 0 if the bit in m (hl) specified if [m (hl),t2] by the immediate data t 1 t 0 = 0 is zero. internal control registers can also be tested by pc7 to 0 ? branch to the location in the executing this p 7 p 6 p 5 p 4 same page specified by p 7 to instruction bpt2 branch on port bit 1101 10t 1 t 0 22 p 3 p 2 p 1 p 0 p 0 if the bit in port (dp l ) immediately after addr p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 if [p (dp l ), t2] specified by the immediate a bank = 1 data t 1 t 0 is one. instruction. however, this is limited to registers that can be read out. internal control registers can also be tested by pc7 to 0 ? branch to the location in the executing this p 7 p 6 p 5 p 4 same page specified by p 7 to instruction bnpt2 branch on no port bit 1001 10t 1 t 0 22 p 3 p 2 p 1 p 0 p 0 if the bit in port (dp l ) immediately after addr p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 if [p (dp l ), t2] specified by the immediate a bank = 0 data t 1 t 0 is zero. instruction. however, this is limited to registers that can be read out. number of bytes number of cycles continued on next page. reg i 1 i 0 hl 0 0 xy 0 1 ae 1 0 illegal value 1 1
continued from preceding page. no. 5483-23/25 lc662304a, 662306a, 662308a, 662312a, 662316a continued on next page. instruction code affected mnemonic operation description status note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bits [branch instructions] pc7 to 0 ? branch to the location in the bc addr branch on cf 1101 1100 22 p 7 p 6 p 5 p 4 same page specified by p 7 to p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 p 3 p 2 p 1 p 0 p 0 if cf is one. if (cf) = 1 pc7 to 0 ? branch to the location in the bnc branch on no cf 1001 1100 22 p 7 p 6 p 5 p 4 same page specified by p 7 to addr p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 p 3 p 2 p 1 p 0 p 0 if cf is zero. if (cf) = 0 pc7 to 0 ? branch to the location in the bz addr branch on zf 1101 1101 22 p 7 p 6 p 5 p 4 same page specified by p 7 to p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 p 3 p 2 p 1 p 0 p 0 if zf is one. if (zf) = 1 pc7 to 0 ? branch to the location in the bnz branch on no zf 1001 1100 22 p 7 p 6 p 5 p 4 same page specified by p 7 to addr p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 p 3 p 2 p 1 p 0 p 0 if zf is zero. if (zf) = 0 pc7 to 0 ? branch to the location in the bfn4 1111 n 3 n 2 n 1 n 0 p 7 p 6 p 5 p 4 same page specified by p 0 to addr branch on flag bit p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 22 p 3 p 2 p 1 p 0 p 7 if the flag (of the 16 user if (fn) = 1 flags) specified by n 3 n 2 n 1 n 0 is one. pc7 to 0 ? branch to the location in the bnfn4 1011 n 3 n 2 n 1 n 0 p 7 p 6 p 5 p 4 same page specified by p 0 to addr branch on no flag bit p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 22 p 3 p 2 p 1 p 0 p 7 if the flag (of the 16 user if (fn) = 0 flags) specified by n 3 n 2 n 1 n 0 is zero. [i/o instructions] ip0 input port 0 to ac 0010 0000 1 1 ac ? (p0) input the contents of port zf 0 to ac. ip input port to ac 0010 0110 1 1 ac ? [p (dp l )] input the contents of port zf p (dp l ) to ac. ipm input port to m 0001 1001 1 1 m (hl) ? [p (dp l )] input the contents of port p (dp l ) to m (hl). ipdr i4 input port to 1100 1111 2 2 ac ? [p (i4)] input the contents of zf ac direct 0110 i 3 i 2 i 1 i 0 p (i4) to ac. input port 4, 5 to 1100 1111 e ? [p (4)] input the contents of ports ip45 e, ac respectively 1101 0100 22 ac ? [p (5)] p (4) and p (5) to e and ac respectively. op output ac to port 0010 0101 1 1 p (dp l ) ? (ac) output the contents of ac to port p (dp l ). opm output m to port 0001 1010 1 1 p (dp l ) ? [m (hl)] output the contents of m (hl) to port p (dp l ). opdr i4 output ac to 1100 1111 2 2 p (i4) ? (ac) output the contents of ac port direct 0111 i 3 i 2 i 1 i 0 to p (i4). output e, ac to port 1100 1111 p (4) ? (e) output the contents of e and op45 4, 5 respectively 1101 0101 22 p (5) ? (ac) ac to ports p (4) and p (5) respectively. set to one the bit in port spb t2 set port bit 0000 10t 1 t 0 1 1 [p (dp l ), t2] ? 1 p (dp l ) specified by the immediate data t 1 t 0 . clear to zero the bit in port rpb t2 reset port bit 0010 10t 1 t 0 1 1 [p (dp l ), t2] ? 0 p (dp l ) specified by the zf immediate data t 1 t 0 . and port with p (p 3 to p 0 ) ? take the logical and of p (p 3 andpdr immediate data then 1100 0101 2 2 [p (p 3 to p 0 )] to p 0 ) and the immediate data zf i4, p4 output i 3 i 2 i 1 i 0 p 3 p 2 p 1 p 0 i 3 to i 0 i 3 i 2 i 1 i 0 and output the result to p (p 3 to p 0 ). or port with p (p 3 to p 0 ) ? take the logical or of p (p 3 orpdr immediate data then 1100 0100 2 2 [p (p 3 to p 0 )] to p 0 ) and the immediate data zf i4, p4 output i 3 i 2 i 1 i 0 p 3 p 2 p 1 p 0 i 3 to i 0 i 3 i 2 i 1 i 0 and output the result to p (p 3 to p 0 ). number of bytes number of cycles
continued from preceding page. no. 5483-24/25 lc662304a, 662306a, 662308a, 662312a, 662316a instruction code affected mnemonic operation description status note d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bits [timer control instructions] timer0 ? [m2 (hl)], write the contents of m2 (hl), wttm0 write timer 0 1100 1010 1 2 (ac) ac into the timer 0 reload register. 1100 1111 write the contents of e, ac wttm1 write timer 1 1111 0100 2 2 timer1 ? (e), (ac) into the timer 1 reload register a. m2 (hl), read out the contents of the rtim0 read timer 0 1100 1011 1 2 ac ? (timer0) timer 0 counter into m2 (hl), ac. rtim1 read timer 1 1100 1111 2 2 e, ac ? (timer1) read out the contents of the 1111 0101 timer 1 counter into e, ac. start0 start timer 0 1100 1111 2 2 start timer 0 counter start the timer 0 counter. 1110 0110 start1 start timer 1 1100 1111 2 2 start timer 1 counter start the timer 1 counter. 1110 0111 stop0 stop timer 0 1100 1111 2 2 stop timer 0 counter stop the timer 0 counter. 1111 0110 stop1 stop timer 1 1100 1111 2 2 stop timer 1 counter stop the timer 1 counter. 1111 0111 [interrupt control instructions] mset set interrupt master 1100 1101 2 2 mse ? 1 set the interrupt master enable flag 0101 0000 enable flag to one. mreset reset interrupt 1100 1101 2 2 mse ? 0 clear the interrupt master master enable flag 1001 0000 enable flag to zero. eih i4 enable interrupt high 1100 1101 2 2 edih ? (edih) i4 set the interrupt enable flag 0101 i 3 i 2 i 1 i 0 to one. eil i4 enable interrupt low 1100 1101 2 2 edil ? (edil) i4 set the interrupt enable flag 0100 i 3 i 2 i 1 i 0 to one. dih i4 disable interrupt high 1100 1101 2 2 edih ? (edih) i4 clear the interrupt enable zf 1001 i 3 i 2 i 1 i 0 flag to zero. dil i4 disable interrupt low 1100 1101 2 2 edil ? (edil) i4 clear the interrupt enable zf 1000 i 3 i 2 i 1 i 0 flag to zero. wtsp write sp 1100 1111 2 2 sp ? (e), (ac) transfer the contents of e, 1101 1010 ac to sp. rsp read sp 1100 1111 2 2 e, ac ? (sp) transfer the contents of sp 1101 1011 to e, ac. [standby control instructions] halt halt 1100 1111 2 2 halt enter halt mode. 1101 1110 hold hold 1100 1111 2 2 hold enter hold mode. 1101 1111 [serial i/o control instructions] starts start serial i o 1100 1111 2 2 start si o start sio operation. 1110 1110 wtsio write serial i o 1100 1111 2 2 sio ? (e), (ac) write the contents of e, 1110 1111 ac to sio. rsio read serial i o 1100 1111 2 2 e, ac ? (sio) read the contents of sio 1111 1111 into e, ac. [other instructions] consume one machine cycle nop no operation 0000 0000 1 1 no operation without performing any operation. sb i2 select bank 1100 1111 2 2 pc13, pc12 ? i 1 i 0 specify the memory bank. 1100 00i 1 i 0 number of bytes number of cycles
no. 5483-25/25 lc662304a, 662306a, 662308a, 662312a, 662316a this catalog provides information as of february, 1997. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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